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ltc2751 1 2751fa c2 150pf + ? 1/2 lt ? 1469 ? + 1/2 lt1469 16-bit dac with span select ltc2751-16 r vos r com r in r2 r1 r ofs ref 5v 5v ref r fb i out1 v out i out2 gnd wr upd read d/s clr mspan span i/o s2-s0 c1 15pf v dd 2751 ta01 wr upd read d/s clr c3 0.1f 3 data i/o d15-d0 16 typical a pplica t ion fea t ures a pplica t ions descrip t ion current output 12-/14-/16-bit softspan dacs with parallel i/o the lt c ? 2751 is a family of 12-, 14-, and 16- bit multi- plying parallel-input, current-output dacs. they operate from a single 2.7 v to 5.5 v supply. all parts are guaranteed monotonic over temperature. the ltc2751a-16 provides 16-bit performance (1lsb inl and dnl) over temperature without any adjustments. these softspan? dacs offer six output ranges two unipolar and four bipolar that can be programmed through the parallel interface, or pinstrapped for operation in a single range. these parts use a bidirectional input/output parallel in- terface that allows readback of any on-chip register. a power- on circuit resets the dac output to 0 v when power is initially applied. a logic low on the clr pin asynchronously clears the dac to 0v in any output range. the parts are specified over commercial and industrial temperature ranges. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 16-bit dac with software selectable ranges n six programmable output ranges unipolar: 0v to 5v, 0v to 10v bipolar: 5v, 10v, 2.5v, C2.5v to 7.5v n maximum 16- bit inl error: 1 lsb over temperature n low 1a (maximum) supply current n guaranteed monotonic over t emperature n low glitch impulse 1nv ? s n 2.7v to 5.5v single supply operation n 2 s settling time to 1 lsb n reference input: 15v n parallel interface with readback of all registers n asynchronous clr pin clears dac output to 0v in any output range n power-on reset to 0v n 38-pin 5mm 7mm qfn package n high resolution offset and gain adjustment n process control and industrial automation n automatic test equipment n data acquisition systems ltc2751-16 integral nonlinearity code 0 ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 16384 32768 ?0.6 0.6 0.8 0.2 49152 65535 2751 ta01b 25c 90c ?45c v dd = 5v v ref = 5v 10v range
ltc2751 2 2751fa 13 14 15 16 top view 39 ltc2751-12 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1r com r in s2 i out2 nc d11 d10 d9 d8 d7 d6 d5 wr upd read d/s nc nc nc nc nc nc d0 d1 ref r ofs r fb i out1 r vos s1 s0 d4 d3 v dd gnd clr mspan d2 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb 13 14 15 16 top view 39 ltc2751-14 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1r com r in s2 i out2 nc d13 d12 d11 d10 d9 d8 d7 wr upd read d/s nc nc nc nc d0 d1 d2 d3 ref r ofs r fb i out1 r vos s1 s0 d6 d5 v dd gnd clr mspan d4 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb 13 14 15 16 top view 39 ltc2751-16 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1r com r in s2 i out2 nc d15 d14 d13 d12 d11 d10 d9 wr upd read d/s nc nc d0 d1 d2 d3 d4 d5 ref r ofs r fb i out1 r vos s1 s0 d8 d7 v dd gnd clr mspan d6 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w exposed pad (pin 39) is gnd, must be soldered to pcb a bsolu t e maxi m u m r a t ings i out 1 , i out 2 , r com to gnd ..................................... 0.3 v r fb , r ofs , r in , ref , r vos to gnd ........................... 1 5 v v dd to gnd .................................................. C 0.3 v to 7v s 2, s 1, s 0, d 15- d 0, mspan , read , d /s, wr , upd , clr to gnd ........ C 0.3 v to v dd + 0.3 v (7 v max ) (notes 1, 2) p in c on f igura t ion o r d er i n f or m a t ion operating temperature range ltc 2751 c ..................................................... 0 c to 70 c ltc 2751 i .................................................. C 40 c to 85 c maximum junction temperature .......................... 12 5 c storage temperature range .................. C 65 c to 150 c lead free finish tape and reel part marking* package description temperature range ltc2751cuhf-12#pbf ltc2751cuhf-12#trpbf 275112 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2751iuhf-12#pbf ltc2751iuhf-12#trpbf 275112 38-lead (5mm 7mm) plastic qfn C40c to 85c ltc2751cuhf-14#pbf ltc2751cuhf-14#trpbf 275114 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2751iuhf-14#pbf ltc2751iuhf-14#trpbf 275114 38-lead (5mm 7mm) plastic qfn C40c to 85c ltc2751bcuhf-16#pbf ltc2751bcuhf-16#trpbf 275116 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2751biuhf-16#pbf ltc2751biuhf-16#trpbf 275116 38-lead (5mm 7mm) plastic qfn C40c to 85c ltc2751acuhf-16#pbf ltc2751acuhf-16#trpbf 275116 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc2751aiuhf-16#pbf ltc2751aiuhf-16#trpbf 275116 38-lead (5mm 7mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc2751 3 2751fa e lec t rical c harac t eris t ics v dd = 5v, v ref = 5v unless otherwise specified. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions ltc2751-12 ltc2751-14 ltc2751b-16 ltc2751a-16 units min typ max min typ max min typ max min typ max static performance resolution l 12 14 16 16 bits monotonicity l 12 14 16 16 bits dnl differential nonlinearity l 1 1 1 0.2 1 lsb inl integral nonlinearity l 1 1 2 0.4 1 lsb ge gain error all output ranges l 0.5 2 1.5 5 20 4 14 lsb ge tc gain error temp- erature coefficient dgain/d temp 0.6 0.6 0.6 0.6 ppm/c bze bipolar zero error all bipolar ranges l 0.2 1 0.6 3 12 2 8 lsb bzs tc bipolar zero temp- erature coefficient 0.5 0.5 0.5 0.5 ppm/c psr power supply rejection v dd = 5v, 10% v dd = 3v, 10% l l 0.025 0.06 0.1 0.25 0.4 1 0.03 0.1 0.2 0.5 lsb/v i lkg i out1 leakage current t a = 25c t min to t max l 0.05 2 5 0.05 2 5 0.05 2 5 0.05 2 5 na c iout1 output capacitance full-scale zero scale 75 45 75 45 75 45 75 45 pf pf symbol parameter conditions min typ max units resistances (note 3) r1/r2 reference inverting resistors (note 4) l 16 20 kw r ref dac input resistance l 8 10 kw r fb feedback resistor (note 3) l 8 10 kw r ofs bipolar offset resistor (note 3) l 16 20 kw r vos offset adjust resistor l 800 1000 kw dynamic performance output settling time 0v to 10v range, 10v step. to 0.0015% fs (note 5) 2 s glitch impulse (note 6) 1 nv ? s digital-to-analog glitch impulse (note 7) 1 nv ? s multiplying feedthrough error 0v to 10v range, v ref = 10v, 10khz sine wave 0.5 mv thd total harmonic distortion (note 8) multiplying C110 db output noise voltage density (note 9) at i out1 13 nv/hz power supply v dd supply voltage l 2.7 5.5 v i dd supply current, v dd digital inputs = 0v or v dd l 0.5 1 a v dd = 5v, v ref = 5v unless otherwise specified. the l denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25c.
ltc2751 4 2751fa symbol parameter conditions min typ max units digital inputs v ih digital input high voltage 3.3v v dd 5.5v 2.7v v dd < 3.3v l l 2.4 2 v v v il digital input low voltage 4.5v < v dd 5.5v 2.7v v dd 4.5v l l 0.8 0.6 v v i in digital input current v in = gnd to v dd l 1 a c in digital input capacitance v in = 0v (note 10) l 6 pf digital outputs v oh i oh = 200a l v dd C 0.4 v v ol i ol = 200a l 0.4 v ti m ing c harac t eris t ics v dd = 5v, v ref = 5v unless otherwise specified. the l denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units v dd = 4.5v to 5.5v write and update timing t 1 i/o valid to wr rising edge set-up l 9 ns t 2 i/o valid to wr rising edge hold l 9 ns t 3 wr pulse width l 20 ns t 4 upd pulse width l 20 ns t 5 upd falling edge to wr falling edge no data shoot-through l 0 ns t 6 wr rising edge to upd rising edge (note 10) l 0 ns t 7 d /s valid to wr falling edge set-up time l 9 ns t 8 wr rising edge to d /s valid hold time l 9 ns readback timing t 13 wr rising edge to read rising edge l 9 ns t 14 read falling edge to wr falling edge (note 10) l 20 ns t 15 read rising edge to i/o propagation delay c l = 10pf l 30 ns t 17 upd valid to i/o propagation delay c l = 10pf l 30 ns t 18 d /s valid to read rising edge (note 10) l 9 ns t 19 read rising edge to upd rising edge no update l 9 ns t 20 upd falling edge to read falling edge no update l 9 ns t 22 read falling edge to upd rising edge (note 10) l 9 ns t 23 i/o bus hi-z to read rising edge (note 10) l 0 ns t 24 read falling edge to i/o bus active (note 10) l 20 ns clr timing t 25 clr pulse width low l 20 ns e lec t rical c harac t eris t ics v dd = 5v, v ref = 5v unless otherwise specified. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c.
ltc2751 5 2751fa symbol parameter conditions min typ max units v dd = 2.7v to 3.3v write and update timing t 1 i/o valid to wr rising edge set-up l 18 ns t 2 i/o valid to wr rising edge hold l 18 ns t 3 wr pulse width l 30 ns t 4 upd pulse width l 30 ns t 5 upd falling edge to wr falling edge no data shoot-through l 0 ns t 6 wr rising edge to upd rising edge (note 10) l 0 ns t 7 d /s valid to wr falling edge set-up time l 18 ns t 8 wr rising edge to d /s valid hold time l 18 ns readback timing t 13 wr rising edge to read rising edge l 18 ns t 14 read falling edge to wr falling edge (note 10) l 40 ns t 15 read rising edge to i/o propagation delay c l = 10pf l 40 ns t 17 upd valid to i/o propagation delay c l = 10pf l 40 ns t 18 d /s valid to read rising edge (note 10) l 18 ns t 19 read rising edge to upd rising edge no update l 9 ns t 20 upd falling edge to read falling edge no update l 9 ns t 22 read falling edge to upd rising edge (note 10) l 18 ns t 23 i/o bus hi-z to read rising edge (note 10) l 0 ns t 24 read falling edge to i/o bus active (note 10) l 40 ns clr timing t 25 clr pulse width low l 30 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the specified maximum operating junction temperature may impair device reliability. note 3 : because of the proprietary softspan switching architecture, the measured resistance looking into each of the specified pins is constant for all output ranges if the i out1 and i out2 pins are held at ground. note 4: r1 is measured from r in to r com ; r2 is measured from ref to r com . note 5: using lt1469 with c feedback = 15pf. a 0.0015% settling time of 1.7s can be achieved by optimizing the time constant on an individual t i m ing c harac t eris t ics v dd = 5v, v ref = 5v unless otherwise specified. the l denotes specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25c. basis. see application note 74, component and measurement advances ensure 16-bit dac settling time. note 6: measured at the major carry transition, 0v to 5v range. output amplifier: lt1469; c fb = 27pf. note 7. full-scale transition; ref = 0v. note 8. ref = 6v rms at 1khz. 0v to 5v range. dac code = fs. output amplifier = lt1469. note 9. calculation from v n = 4ktrb, where k = 1.38e-23 j/k (boltzmann constant), r = resistance (w), t = temperature (k), and b = bandwidth (hz). note 10. guaranteed by design. not production tested.
ltc2751 6 2751fa v ref (v) ?10 ?8 0 4 4 ?6 2 2 6 8 10 2751 g09 v dd = 5v 5v range ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 ?0.6 0.6 0.8 0.2 +dnl ?dnl +dnl ?dnl code 0 ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 16384 32768 ?0.6 0.6 0.8 0.2 49152 65535 2751 g01 v dd = 5v v ref = 5v 10v range code 0 ?1.0 dnl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 16384 32768 ?0.6 0.6 0.8 0.2 49152 65535 2751 g02 v dd = 5v v ref = 5v 10v range temperature (c) ?40 ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 ?20 20 0 40 ?0.6 0.6 0.8 0.2 60 80 2751 g04 v dd = 5v v ref = 5v 10v range +inl ?inl temperature (c) ?40 ?1.0 dnl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 ?20 20 0 40 ?0.6 0.6 0.8 0.2 60 80 2751 g05 v dd = 5v v ref = 5v 10v range +dnl ?dnl temperature (c) ?40 bze (lsb) 8 4 2 0 4 ?20 20 0 40 6 6 8 2 60 80 2751 g06 v dd = 5v v ref = 5v 10v range 0.5ppm/c (typ) temperature (c) ?40 ge (lsb) ?16 ?8 ?4 0 8 ?20 20 0 40 ?12 12 16 4 60 80 2751 g07 v dd = 5v v ref = 5v 10v range 0.6ppm/c (typ) v ref (v) ?10 ?8 0 4 4 ?6 2 2 6 8 10 2751 g08 v dd = 5v 5v range ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 ?0.6 0.6 0.8 0.2 +inl ?inl +inl ?inl inl vs temperature dnl vs temperature bipolar zero vs temperature gain error vs temperature inl vs v ref dnl vs v ref typical p er f or m ance c harac t eris t ics integral nonlinearity (inl) differential nonlinearity (dnl) ltc2751-16 t a = 25c, unless otherwise noted.
ltc2751 7 2751fa 500ns/div upd 5v/div gated settling waveform 250v/div 2751 g10 using lt1469 amp c feedback = 12pf 0v to 10v step code 0 ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 4096 8192 ?0.6 0.6 0.8 0.2 12288 16383 2751 g11 v dd = 5v v ref = 5v 10v range code 0 ?1.0 dnl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 4096 8192 ?0.6 0.6 0.8 0.2 12288 16383 2751 g12 v dd = 5v v ref = 5v 10v range code 0 ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 1024 2048 ?0.6 0.6 0.8 0.2 3072 4095 2751 g13 v dd = 5v v ref = 5v 10v range code 0 dnl (lsb) 1024 2048 3072 4095 2751 g14 v dd = 5v v ref = 5v 10v range ?1.0 ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 ?0.6 0.6 0.8 0.2 typical p er f or m ance c harac t eris t ics settling 0v to 10v integral nonlinearity (inl) differential nonlinearity (dnl) ltc2751-12 ltc2751-16 integral nonlinearity (inl) differential nonlinearity (dnl) ltc2751-14 v dd (v) 2.5 ?1.0 inl (lsb) ? 0.8 ?0.4 ?0.2 0.0 1.0 0.4 3 4 3.5 4.5 ?0.6 0.6 0.8 0.2 5 5.5 2751 g09b +inl ?inl inl vs v dd t a = 25c, unless otherwise noted.
ltc2751 8 2751fa 500ns/div upd 5v/div v out 2mv/div 2751 g15 using an lt1469 c feedback = 27pf v dd = 5v v ref = 5v 0v to 5v range 1nv ? s (typ) logic voltage (v) 0 1 0 i dd (ma) 2 4 6 8 10 12 2 3 4 5 2751 g16 all digital pins tied together (except read tied to gnd) v dd = 5v v dd = 3v v dd (v) 2.5 0.5 logic threshold (v) 0.75 1 1.25 1.5 2 3 3.5 4 4.5 5 5.5 1.75 2751 g17 rising falling upd frequency (hz) 10 supply current (a) 10 100 100k 1 0.1 100 1k 10k 1m 1000 2751 g18 v dd = 5v v dd = 3v alternating zero-scale/full-scale (ltc2751-16) midscale glitch logic threshold vs supply voltage supply current vs logic input voltage supply current vs update frequency typical p er f or m ance c harac t eris t ics ltc2751-12, ltc2751-14, ltc2751-16 t a = 25c, unless otherwise noted.
ltc2751 9 2751fa p in func t ions r com (pin 1): center tap point of r in and ref. normally tied to the negative input of the external reference invert- ing amplifier. r in (pin 2): input resistor for external reference inverting amplifier. normally tied to the external reference voltage v ref and to r ofs ( pin 37). typically 5 v ; accepts up to 15 v. s2 (pin 3): span i/o bit 2. pins s0, s1 and s2 are used to program and to read back the output range of the dac. i out2 ( pin 4): dac current output complement. tie i out2 to gnd. nc (pin 5): no connection. must be tied to gnd, provides necessary shielding for i out2 . d 3-d11 (pins 6-14): ltc2751-12 only. dac input/ output data bits. these i/o pins set and read back the dac code. d11 is the msb. d 5-d13 (pins 6-14): ltc2751-14 only. dac input/ output data bits. these i/o pins set and read back the dac code. d13 is the msb. d 7-d15 (pins 6-14): ltc2751-16 only. dac input/ output data bits. these i/o pins set and read back the dac code. d15 is the msb. v dd (pin 15): positive supply input 2.7v v dd 5.5v. requires a 0.1f bypass capacitor to gnd. gnd (pin 16): ground. tie to ground. clr (pin 17): asynchronous clear. when clr is taken to a logic low, the data registers are reset to the zero-volt code for the present output range (v out = 0v). mspan ( pin 18): manual span control pin. mspan is used to configure the ltc2751 for operation in a single, fixed output range. when configured for single-span operation, the output range is set via hardware pin strapping. the span input and dac registers are transparent and do not respond to write or update commands. to configure the part for single-span use, tie mspan directly to v dd . if mspan is instead connected to gnd (softspan configuration), the output ranges are set and verified by using write, update and read operations. see manual span configuration in the operation section. mspan must be connected either directly to gnd (soft- span configuration) or v dd (single-span configuration). d 0-d2 (pins 19-21): ltc2751-12 only. dac input/ output data bits. these i/o pins set and read back the dac code. d0 is the lsb. d 0-d4 (pins 19-23): ltc2751-14 only. dac input/ output data bits. these i/o pins set and read back the dac code. d0 is the lsb. d 0- d6 (pins 19-25): ltc2751-16 only. dac input/ output data bits. these i/o pins set and read back the dac code. d0 is the lsb. nc (pins 22-27): ltc2751-12 only. no connection. nc (pins 24-27): ltc2751-14 only. no connection. nc (pins 26, 27): ltc2751-16 only. no connection. d/s (pin 28): data/span select. this pin is used to select activation of the data or span i/o pins ( d0 to d15 or s0 to s2, respectively), along with their respective dedicated registers, for write or read operations. update operations ignore d /s, since all updates affect both data and span registers. for single-span operation, tie d/s to gnd. read (pin 29): read pin. when read is asserted high, the data i/o pins ( d0-d15) or span i/o pins ( s0-s2) output the contents of the selected register ( see table 1). for single- span operation, readback of the span i/o pins is disabled. upd (pin 30): update and buffer select pin. when read is held low and upd is asserted high, the contents of the input registers ( both data and span) are copied into their respective dac registers. the output of the dac is updated, reflecting the new dac register values. when read is held high, the update function is disabled and the upd pin functions as a buffer selectorlogic low to select the input register, high for the dac register. see readback in the operation section. wr (pin 31): active low write pin. a write operation copies the data present on the data or span i/o pins (d0- d15 or s0-s2, respectively) into the input register. when read is high, the write function is disabled. s0 (pin 32): span i/o bit 0. pins s0, s1 and s2 are used to program and to read back the output range of the dac.
ltc2751 10 2751fa p in func t ions s1 (pin 33): span i/o bit 1. pins s0, s1 and s2 are used to program and to read back the output range of the dac. r vos (pin 34): dac offset adjust. nominal input range is 5v. if not used, r vos should be shorted to i out2 . i out1 (pin 35): dac current output; normally tied to the negative input of the i/v converter amplifier. r fb (pin 36): dac feedback resistor; normally tied to the output of the i/v converter amplifier. the dac output current from i out1 flows through the feedback resistor to the r fb pin. r ofs (pin 37): bipolar offset network. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15 v; normally tied to the positive reference voltage at r in (pin 2). ref ( pin 38): feedback resistor for the reference inverting amplifier, and reference input for the dac. normally tied to the output of the reference inverting amplifier. typically C5v. accepts up to 15v. exposed pad (pin 39): ground. the exposed pad must be soldered to the pcb.
ltc2751 11 2751fa b lock diagra m 29 31 30 28 17 18 16-bit dac with span select dac register input register r com r in r2 r1 r ofs ref r fb i out1 i out2 read wr upd d/s clr mspan 2751 bd control logic 3 3 3 i/o port dac register input register 16 16 16 i/o port 35 36 37 38 1 2 4 3, 32, 33 span i/o s2-s0 6-14, 19-25 data i/o d15-d0
ltc2751 12 2751fa output ranges the ltc2751 is a current-output, parallel-input precision multiplying dac with software- programmable output ranges. softspan provides two unipolar output ranges (0v to 5 v and 0 v to 10 v), and four bipolar ranges (2.5v, 5v, 10 v and C2.5 v to 7.5 v). these ranges are obtained when an external precision 5 v reference is used. when a reference voltage of 2 v is used, the softspan ranges become: 0 v to 2v, 0 v to 4v, 1v, 2v, 4 v and C1 v to 3v. the output ranges are linearly scaled for references other than 2v and 5v. ti m ing diagra m s o pera t ion digital section the ltc2751 family has four internal interface registers (see block diagram). tw o of theseone input and one dac registerare dedicated to the data i/o port, and two to the span i/o port. each port is thus double-buffered. the double-buffered feature provides the capability to simultaneously update the span and code, which allows smooth voltage transitions when changing output ranges. it also permits the simultaneous updating of multiple dacs. clr wr 2751 td01 t 3 t 6 t 5 t 7 t 8 t 4 t 2 t 1 i/o input upd d/s t 25 wr 2751 td02 i/o output i/o input read upd d/s t 13 t 23 t 15 t 19 t 17 t 20 t 22 t 18 t 14 t 24 write, update and clear timing readback timing
ltc2751 13 2751fa o pera t ion table 1 shows the functions of the ltc2751. table 1. write, update and read functions read d/s wr upd span i/o d ata i/o 0 0 0 0 - write to input register 0 0 0 1 - write/update (transparent) 0 0 1 0 - - 0 0 1 1 update dac register update dac register 0 1 0 0 write to input register - 0 1 0 1 write/update (transparent) - 0 1 1 0 - - 0 1 1 1 update dac register update dac register 1 0 x 0 - read input register 1 0 x 1 - read dac register 1 1 x 0 read input register - 1 1 x 1 read dac register - x = dont care manual span configuration multiple output ranges are not needed in some applications. to configure the ltc2751 for single- span operation, tie the mspan pin to v dd and the d /s pin to gnd. the desired output range is then specified by the span i/o pins ( s0, s1 and s2) as usual, but the pins are programmed by tying directly to gnd or v dd (see figure 1 and table 2). in this configuration, the part will initialize to the chosen output range at power-up, with v out = 0v. when configured for manual span operation, span pin readback is disabled. write and update operations the data input register is loaded directly from a 16-bit microprocessor bus by holding the d/s pin low and then pulsing the wr pin low. the second register ( dac regis- ter) is loaded by pulsing the upd pin high, which copies the data held in the input register into the dac register. note that updates always include both data and span; but the dac register values will not change unless the input register values have been changed by writing. loading the span input register is accomplished in a similar manner, by holding the d /s pin high and then bringing the wr pin low. the span and data register structures are the same except for the number of parallel bitsthe span registers have three bits, while the data registers have 12, 14, or 16 bits. to make both registers transparent for flowthrough mode, tie wr low and upd high. however, this defeats the de- glitcher operation and output glitch impulse may increase. the deglitcher is activated on the rising edge of the upd pin. the interface also allows the use of the input and dac registers in a master-slave, or edge-triggered, configura- tion. this mode of operation occurs when wr and upd are tied together and driven by a single clock signal. the data bits are loaded into the input register on the falling edge of the clock and then loaded into the dac register on the rising edge. the separation of data and span for write and read opera- tions makes it possible to control both data and span on one 16- bit wide data bus by allowing span pins s2 to s0 to share bus lines with the data lsbs ( d2 to d0). since no write or read operation includes both span and data, there cannot be a conflict. the asynchronous clear pin resets the ltc2751 to 0v (zero-, half- or quarter-scale code) in any output range. clr resets both the input and dac data registers, while leaving the span registers undisturbed. these devices also have a power-on reset. if configured for softspan operation, the part initializes to zero scale in the 0 v to 5 v output range. if configured for single-span operation, the part initializes to the zero-volt code in the chosen output range. figure 1. configuring the ltc2751 for single-span operation (10v range) ltc2751-16 mspan s2 s1 s0 d/s v dd 2751 f01 wr upd read data i/o 16 v dd
ltc2751 14 2751fa o pera t ion is a two-function pin. the update function is disabled when read is high, and the upd pin instead selects the input or dac register for readback. table 1 shows the readback functions for the ltc2751. the most common readback task is to check the contents of an input register after writing to it, before updating the new data to the dac register. to do this, bring read high while holding upd low. the contents of the selected ports input register are output by the data or span i/o pins. to read back the contents of a dac register, bring read high, then bring upd high. the contents of the selected data or span dac register are output by the data or span i/o pins. note: if no update is desired after the readback operation, upd must be returned low before bringing read low, otherwise the upd pin will revert to its primary function and update the dac. system offset adjustment many systems require compensation for overall system offset. the r vos offset adjustment pin is provided for this purpose. for noise immunity and ease of adjustment, the control voltage is attenuated to the dac output: v os = C0.01 ? v(r vos ) [0v to 5v, 2.5v spans] v os = C0.02 ? v(r vos ) [0v to 10v, 5v, C2.5v to 7.5v spans] v os = C0.04 ? v(r vos ) [10v span] the nominal input range of this pin is 5 v; other refer- ence voltages of up to 15 v may be used if needed. the r vos pin has an input impedance of 1mw. to preserve the settling performance of the ltc2751, this pin should be driven with a thevenin-equivalent impedance of 10kw or less. if not used, r vos should be shorted to i out2 . table 2. span codes s2 s1 s0 span 0 0 0 unipolar 0v to 5v 0 0 1 unipolar 0v to 10v 0 1 0 bipolar C5v to 5v 0 1 1 bipolar C10v to 10v 1 0 0 bipolar C2.5v to 2.5v 1 0 1 bipolar C2.5v to 7.5v codes not shown are reserved and should not be used. readback the contents of any one of the four interface registers can be read back by using the read pin in conjunction with the d/s and upd pins. a readback operation is initiated by bringing read to logic high. the i/o pins, which are high- impedance digital inputs when read is low, selectively change to low-impedance logic outputs during readback. the i/o pins comprise two ports, data and span. the data i/o port consists of pins d0-d11, d0-d13 or d0-d15 (ltc2751-12, ltc2751-14 or ltc2751-16, respectively). the span i/o port consists of pins s0, s1 and s2 for all parts. each i/o port has one dedicated input register and one dedicated dac register. the register structure is shown in the block diagram. the d /s pin is used to select which i/o port ( data or span) is configured to read back the contents of its registers . the unselected i/o ports pins remain high-impedance inputs. once the i/o port is selected, its input or dac register is selected for readback by using the upd pin. note that upd
ltc2751 15 2751fa o pera t ion e xa m ples wr 2751 td03 span i/o input data i/o input upd d/s 8000 h 010 read = low update (5v range, v out = 0v) wr 2751 td04 span i/o input data i/o input read = low upd d/s c000 h 4000 h 011 update (5v) update (?5v) wr 2751 td05 data i/o output data i/o input read upd d/s 8000 h 8000 h 0000 h hi-z input register dac register hi-z update (2.5v) 1. load 5 v range with the output at 0 v. note that since span and code are updated together, the output, if started at 0v, will stay there. 2. load 10v range with the output at 5v, changing to C5v. 3. write and update mid-scale code in 0 v to 5 v range (v out = 2.5 v) using readback to check the contents of the input and dac registers before updating.
ltc2751 16 2751fa op amp selection because of the extremely high accuracy of the 16-bit ltc2751-16, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 3 and 4 contain equations for evaluating the ef- fects of op amp parameters on the ltc2751s accuracy a pplica t ions i n f or m a t ion when programmed in a unipolar or bipolar output range. these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. tables 3 and 4 can also be used to determine the effects of op amp parameters on the ltc2751-14 and the ltc2751-12. however, the results obtained from tables 3 and 4 are in 16- bit lsbs. divide these results by 4 ( ltc2751-14) and 16 ( ltc2751-12) to obtain the correct lsb sizing. table 5 contains a partial list of lt c precision op amps recommended for use with the ltc2751. the easy-to-use design equations simplify the selection of op amps to meet the systems specified error budget. select the amplifier from table 5 and insert the specified op amp parameters in table 4. add up all the errors for each category to de- termine the effect the op amp has on the accuracy of the part. arithmetic summation gives an ( unlikely) worst-case effect. a root-sum-square ( rms) summation produces a more realistic estimate. ( ) 5v v ref ( ) 5v v ref ( ) 16.5k a vol1 op amp v os1 (mv) i b1 (na) a vol1 (v/v) v os2 (mv) i b2 (mv) a vol2 (v/v) v os1 ? 3.2 ? i b1 ? 0.0003 ?? a1 ? 0 0 0 inl (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 1.5k a vol1 ( ) 66k a vol2 ( ) 131k a vol1 ( ) 131k a vol1 ( ) 131k a vol2 ( ) 131k a vol2 v os1 ? 0.82 ? i b1 ? 0.00008 ?? a2 ? 0 0 0 dnl (lsb) ( ) 5v v ref ( ) 5v v ref a3 ? v os1 ? 13.2 ? i b1 ? 0.13 ?? 0 0 0 0 unipolar offset (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref v os1 ? 13.2 ? i b1 ? 0.0018 ? a5 ? v os2 ? 26.2 ? i b2 ? 0.26 ? bipolar gain error (lsb) ( ) 5v v ref ( ) 5v v ref ( ) ( ) ( ) 5v v ref ( ) 5v v ref a3 ? v os1 ? 19.8 ? i b1 ? 0.13 ?? 0 a4 ? v os2 ? 13.1 ? a4 ? i b2 ? 0.13 ?? a4 ? bipolar zero error (lsb) unipolar gain error (lsb) ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref ( ) 5v v ref v os1 ? 13.2 ? i b1 ? 0.0018 ? a5 ? v os2 ? 26.2 ? i b2 ? 0.26 ? table 3. variables for each output range that adjust the equations in table 4 output range a1 a2 a3 a4 a5 5v 1.1 2 1 1 10v 2.2 3 0.5 1.5 5v 2 2 1 1 1.5 10v 4 4 0.83 1 2.5 2.5v 1 1 1.4 1 1 C2.5v to 7.5v 1.9 3 0.7 0.5 1.5 table 5. partial list of lt c precision amplifiers recommended for use with the ltc2751 with relevant specifications amplifier amplifier specifications v os v i b na a vol v/mv voltage noise nv/hz current noise pa/hz slew rate v/s gain bandwidth product mhz t settling with ltc2751 s power dissipation mw lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 lt1112 (dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/op amp lt1124 (dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/op amp lt1468 75 10 5000 5 0.6 22 90 2 117 lt1469 (dual) 125 10 2000 5 0.6 22 90 2 123/op amp table 4. easy-to-use equations determine op amp effects on dac accuracy in all output ranges (circuit of page 1). subscript 1 refers to output amp, subscript 2 refers to reference inverting amp.
ltc2751 17 2751fa a pplica t ions i n f or m a t ion op amp offset will contribute mostly to output offset and gain error and has minimal effect on inl and dnl. for the ltc2751-16, a 250 v op amp offset will cause about 0.8lsb inl degradation and 0.2 lsb dnl degradation with a 5 v reference. for the ltc2751 programmed in 5v unipolar mode, the same 250 v op amp offset will cause a 3.3lsb zero-scale error and a 3.3lsb gain error. while not directly addressed by the simple equations in tables 3 and 4, temperature effects can be handled just as easily for unipolar and bipolar applications. first, con- sult an op amps data sheet to find the worst-case v os and i b over temperature. then, plug these numbers in the v os and i b equations from table 4 and calculate the temperature-induced effects. for applications where fast settling time is important , application note 74, component and measurement advances ensure 16- bit dac settling time, offers a thorough discussion of 16- bit dac settling time and op amp selection. precision voltage reference considerations much in the same way selecting an operational amplifier for use with the ltc2751 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence . the output voltage of the ltc2751 is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output voltage error. there are three primary error sources to consider when selecting a precision voltage reference for 16- bit appli- cations: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference with low output voltage initial tolerance, like the lt1236 (0.05%), minimizes the gain error caused by the refer- ence; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. a reference s output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuits inl and dnl performance. if a reference is chosen with a loose output voltage temperature coefficient, then the dac output voltage along its transfer characteristic will be very dependent on ambient conditions. minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly con- trolling the ambient temperature of the circuit to minimize temperature gradients . as precision dac applications move to 16- bit and higher performance, reference output voltage noise may contrib- ute a dominant share of the systems noise floor. this in turn can degrade system dynamic range and signal-to- noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practi- cal for the system resolution desired. precision voltage references, like the lt1236, produce low output noise in the 0.1 hz to 10 hz region, well below the 16- bit lsb level in 5 v or 10 v full-scale systems. however, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. table 6. partial list of lt c precision references recommended for use with the ltc2751 with relevant specifications reference initial tolerance temperature drift 0.1hz to 10hz noise lt1019a-5, lt1019a-10 0.05% 5ppm/c 12v p-p lt1236a-5, lt1236a-10 0.05% 5ppm/c 3v p-p lt1460a-5, lt1460a-10 0.075% 10ppm/c 20v p-p lt1790a-2.5 0.05% 10ppm/c 12v p-p grounding as with any high resolution converter, clean grounding is important. a low impedance analog ground plane and star grounding techniques should be used. i out2 must be tied to the star ground with as low a resistance as possible. when it is not possible to locate star ground close to i out2 , a low resistance trace should be used to route this pin to star ground. this minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. when the resistance of this circuit board trace becomes greater than 1w , a force/sense am- plified configuration should be used to drive this pin (see figure 2). this preserves the excellent accuracy (1lsb inl and dnl) of the ltc2751-16.
ltc2751 18 2751fa a pplica t ions i n f or m a t ion + ? 1/2 lt ? 1469 ? + 1/2 lt1469 16-bit dac with span select ltc2751-16 r vos r com 1 r in 2 5 7 6 2 8 1 3 4 r2 r1 38 r ofs 37 ref 5v 5v 15v ref r fb i out1 v out 36 35 i out2 gnd wr upd read d/s clr mspan 4 16 31 30 29 28 17 18 3, 33, 32 c2** 150pf span i/o s2-s0 c1 15pf v dd 15 wr upd read d/s clr c3 0.1f 0.1f 3 6-14, 19-25 34 data i/o d15-d0 16 ? + 6 1 2 3 i out2 2 3 *schottky barrier diode **for multiplying applications c2 = 15pf zetex* bat54s lt1001 2751 f02 1000pf alternate amplifier for optimum settling time performance 6 1 2 3 6 ? + lt1468 3 zetex bat54s 2 200 200 i out2 ?15v 0.1f figure 2. basic connections for softspan v out dac with tw o optional circuits for driving i out2 from gnd with a force/sense amplifier
ltc2751 19 2751fa 7 5 6 1 2 3 c2** 150pf 15v ?15v 8 4 0.1f 0.1f + ? 1/2 lt1469 ? + 1/2 lt1469 16-bit dac with span select ltc2751-16 r vos r com 1 r in 2 r2 r1 38 r ofs 37 ref 5v 5v ref r fb i out1 v out 36 35 i out2 gnd wr upd read d/s clr mspan 4 16 31 30 29 28 17 18 3, 33, 32 span i/o s2-s0 c1 15pf v dd 15 2751 ta02 wr upd read d/s clr c3 0.1f 3 6-14, 19-25 34 data i/o d15-d0 16 **for multiplying applications c2 = 15pf 16-bit dac with software-selectable ranges typical a pplica t ions
ltc2751 20 2751fa p ackage descrip t ion 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c)
ltc2751 21 2751fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 11/12 correction made in the typical application diagram. 1, 18
ltc2751 22 2751fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2007 lt 1112 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt1027 precision reference 2ppm/c maximum drift lt1236a-5 precision reference 0.05% maximum tolerance, 1ppm 0.1hz to 10hz noise lt1468 16-bit accurate op-amp 90mhz gbw, 22v/s slew rate lt1469 dual 16-bit accurate op-amp 90mhz gbw, 22v/s slew rate ltc1588/ltc1589/ ltc1592 serial 12-/14-/16-bit i out single dacs software-selectable (softspan) ranges, 1lsb inl, dnl, 16-lead ssop package ltc1591/ltc1597 parallel 14-/16-bit i out single dac integrated 4-quadrant resistors ltc1821 parallel 16-bit v out single dac 1lsb inl, dnl, 0v to 10v, 0v to C10v, 10v output ranges ltc2601/ltc2611/ ltc2621 serial 12-/14-/16-bit v out single dacs single dacs, spi-compatible, single supply, 0v to 5v outputs in 3mm w 3mm dfn-10 package ltc2606/ltc2616/ ltc2626 serial 12-/14-/16-bit v out single dacs single dacs, i 2 c-compatible, single supply, 0v to 5v outputs in 3mm w 3mm dfn-10 package ltc2641/ltc2642 serial 12-/14-/16-bit unbuffered v out single dacs 2lsb inl, 1lsb dnl, 1s settling, tiny msop-10, 3mm w 3mm dfn-10 packages ltc2704 serial 12-/14-/16-bit v out quad dacs software-selectable (softspan) ranges, integrated amplifiers ? + u2a lt ? 1469 ? + u2b lt1469 ltc2751-16 u1 lt1027 u3 r vos r com r in 2 1 3 8 3 4 2 1 6 7 5 in out trim gnd r ofs 37 v + v + v ? ref r fb i out1 v out 36 35 i out2 data i/o span i/o gnd d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s2 s1 s0 4 34 6 7 8 9 10 11 12 13 14 19 20 21 22 23 24 25 3 33 32 4 2 2 1 6 5 c22 0.001f c1 30pf v dd 2751 ta03 r1 10k wr updread d/s clr mspan 28 29 30 31 17 18 wr updread d/s clr gndgndnc 5 16 39 15 2 1 38 gnd gnd gnd c23 0.1f c20 10f c13 10f gnd gnd r2 10k offset and gain trim circuits. powering v dd from lt1027 ensures quiet supply

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